Cave Creek, Arizona May 14, 2015. The High Density Packaging (HDP) User Group headquartered in the United States is pleased to announce the start of a new project, “Plated through hole (PTH) lifetime predictor for Temperature Cycling (TC)”.

The PTH is the basic building block of circuit interconnect, used in printed circuit boards (PCB) in products we all use every day.

The lifetime of the printed circuit board and your product is very dependent on how long the PTH will last. The PTH reliability is dependent on several variables such as the thickness of the board, the quality and plating in the hole, the thickness of the plating as well as connection interface between the in inner layer and the PTH.

“Right now the conventional approach is to do Accelerated Temperature Cycling to predict the PTH life. BGA/LGA solder joint lifetime, on the other hand, can be predicted using the modified Coffin-Manson Equation. Using such accelerated equation with parameters saves time and cost in predicting the lifetime of interconnects”. Jack Tan the project facilitator at HDP explains.

This project aims to establish an accelerated equation to predict PTH lifetime. This equation can be used to give a more accurate prediction of the product warranty period based on the product’s operating environment. It can also be used to find PTH critical design factors to fine-tune the PTH design at the early PCB design stage, bringing improvement to product lifespan.

This project will focus on PCBs used in telecommunication equipment, computers and servers. FEM will be used to simulate different PTH specifications and operating environments to compute the time to failure of the PTH. Thermal cycle tests will be performed to compare the physical time to failure with the calculated one. This process will be repeated to achieve the optimum result and establish the accelerated equation to predict PTH lifetime for TC.

If you are interested in participating in this project please contact Jack Tan at Jtan@hdpug.org.